1. Field of the Invention
The present invention relates to a liquid crystal display and, more particularly, to an active matrix liquid crystal display.
2. Description of the Prior Art
Presently, liquid crystal displays are extensively used as light and low-power-consuming displays in personal computers and various monitors. In particular, active matrix liquid crystal displays in which a thin film transistor is formed in each pixel are used as high-resolution displays in various applications, because the brightness of each pixel can be finely changed by voltage control.
The structure and operating principle of a conventional general active matrix liquid crystal display (to be referred to as an active matrix display hereinafter) will be described below with reference to FIGS. 1 and 2. FIG. 1 is a sectional view showing this conventional active matrix display. FIG. 2 shows an outline of the circuit configuration of a thin film transistor array formed in a matrix on a first insulating substrate shown in FIG. 1.
In the conventional active matrix display as shown in FIG. 1, first and second insulating substrates 1 and 2 are opposed parallel to each other, and a liquid crystal 10 as a display material is sandwiched between these substrates. A thin film transistor array (FIG. 2) including pixel electrodes 6 is formed on one principal surface of the first insulating substrate 1, which is in contact with the liquid crystal 10.
On one principal surface of the second insulating substrate 2, which is opposed to the first insulating substrate 1 and in contact with the liquid crystal 10, color layers 7, 8, and 9 of three primary colors R (Red), G (Green), and B (Blue) are formed in portions corresponding to the pixel electrodes 6 of the first substrate. A black matrix 11 for intercepting light is formed in the boundaries between these color layers 7, 8, and 9. A common electrode 12 made of a transparent conductive film is formed on the black matrix 11.
FIG. 2 shows an outline of the circuit configuration of the thin film transistor array formed in a matrix on the first insulating substrate shown in FIG. 1. On the principal surface of the first insulating substrate 1, which is in contact with the liquid crystal 10, scanning lines 3 and signal lines 4 are formed in the row and column directions, respectively. Display thin film transistors 5 are formed at the intersections of these scan and signal lines 3 and 4. The gate, drain, and source of each display thin film transistor 5 are connected to the scanning line 3, the signal line 4, and the pixel electrode 6 made of a transparent conductive film, respectively.
In the active matrix display with the above arrangement, a scan pulse voltage for turning on the display thin film transistors 5 is supplied to each scanning line 3. In synchronism with this scan pulse, a signal voltage corresponding to an image to be displayed is supplied to the signal lines 4. Accordingly, the display thin film transistors 5 connected to the scanning line 3 operate, and a predetermined voltage is written in the pixel electrodes 6 from the signal lines 4. The written voltage is held until a scan pulse voltage is supplied to this scanning line 3. Consequently, an electric field corresponding to the held voltage is generated between each pixel electrode 6 and the common electrode 12 (FIG. 1) and changes the alignment of liquid crystal molecules. This changes the amount of light transmitted through the first insulating substrate 1, the liquid crystal 10, and the second insulating substrate 2. The image is displayed by using this change in the light transmission state.
FIGS. 3A to 3E are sectional views showing steps of fabricating a thin film transistor used in the aforementioned conventional active matrix display in order of the steps. The thin film transistor shown in FIGS. 3A to 3E has an inverse stagger structure. As shown in FIG. 3E, an island semiconductor film 16 opposes a gate electrode 14 via a gate insulating film 15. A source electrode 19 and a drain electrode 18 are formed on this semiconductor film 16 via an ohmic contact layer 17.
The fabrication steps of this conventional thin film transistor will be described below with reference to FIGS. 3A to 3E. First, a first conductive film made of Al, Mo, or Cr is deposited on the entire surface of a transparent insulating film 13 such as glass by sputtering or the like. This first conductive film is coated with a photosensitive resist, and exposure, development, etching, and resist removal are performed by photolithography. Consequently, patterning of the first conductive film having a predetermined pattern of, e.g., a gate electrode 14 and a scanning line (not shown) is completed (FIG. 3A).
Subsequently, on the entire surface of the predetermined pattern of the first conductive film, a gate insulating film 15 made of SiO.sub.x or SiN.sub.x, a semiconductor film 16 made of amorphous silicon (to be referred to as "a-Si" hereinafter), and an ohmic contact film 17 made of n-type a-Si or the like are successively formed in this order by sputtering or plasma CVD. After that, photolithography is performed to pattern the semiconductor film 16 and the ohmic contact film 17, forming a predetermined pattern serving as a transistor channel on the gate insulating film 15 above the gate electrode 14 (FIG. 3B).
Next, to electrically connect the first conductive film with a second conductive film for forming a source electrode, a drain electrode, a signal line, and the like by using, e.g., a scanning line input pad and a signal line input pad (neither is shown), the gate insulating film 15 is etched into a predetermined pattern by photolithography to form a hole (not shown) in the gate insulating film 15 above the first conductive film. A second conductive film made of, e.g., Al, Mo, or Cr is deposited on the entire surface by sputtering or the like. A signal line 4 (FIG. 2), a source electrode 19, and a drain electrode 18 are formed by photolithography (FIG. 3C). Additionally, a transparent conductive film made of ITO or the like is deposited on the entire surface, and a pixel electrode 6 is formed by photolithography. After that, etching is performed by using the source electrode 19 and the drain electrode 18 as masks to remove the n-type a-Si, i.e., the ohmic contact film 17 from the transistor channel (FIG. 3D). Finally, a protective film 20 made of SiN.sub.x or the like is deposited (FIG. 3E). Those portions of this protective film, which are on the pixel electrode 6 and the pad for receiving external signals are removed by photolithography, thereby completing the thin film transistor.
In the fabrication process of the thin film transistor array used in this conventional active matrix display, removal charging occurs when the insulating substrate is removed from a tray or the like of the film formation apparatus or the etching apparatus in each step, or the pattern of a conductive film is charged up in, e.g., the film formation step or the etching step. Especially in the insulating film or semiconductor film formation step and the dry etching step using plasma CVD, charging readily occurs because the substrate is exposed to plasma for long time periods. In addition to this charging, abnormal discharging during the film formation step using plasma CVD sometimes instantaneously applies very large electric charge to a certain specific signal line or scanning line.
In a situation like this, as shown in FIG. 2, if the scanning lines 3 or the signal lines 4 are not connected and electrically isolated from each other, it is more likely that the charge amount difference between adjacent scanning lines or signal lines or the electric charge applied to a certain specific scanning line or signal line by abnormal discharging becomes larger than the breakdown voltage of an insulating film. Consequently, a sudden current flows between the adjacent scanning lines or signal lines to cause a defect, e.g., break or short-circuit the lines or break the insulating film. Even if neither breaking of the lines nor a short circuit occurs, electric charge is injected into the gate insulating film in the transistor portion. This changes the transistor characteristics, e.g., shifts the threshold value, resulting in a point defect.
In particular, the pattern of lines such as scanning lines or signal lines initially formed on a transparent insulating substrate, such as scanning lines in this prior art, is subjected to a large number of film formation steps and dry etching steps before the formation of thin film transistors is completed. Additionally, the length and area of the pattern are large. This increases the charge amount by charge-up and increases defects such as breaking of lines and short circuits.
As a thin film transistor array for solving this problem, an active matrix display thin film transistor array in which all scanning lines and all signal lines are connected to common lines is known. FIG. 4 is a plan view showing an outline of the circuit configuration of this thin film transistor array. The thin film transistor array shown in FIG. 4 has the same structure as the inverse stagger thin film transistor shown in FIGS. 3A to 3E.
In the thin film transistor array shown in FIG. 4, scanning lines 3 and signal lines 4 are extracted via scanning line input pads 21 and signal line input pads 22 and connected to a scanning line common line 23 and a signal line common line 24, respectively. In this arrangement, all scanning lines and all signal lines are set at the same potential. Accordingly, even if very large electric charge is applied to a specific scanning line or signal line during the thin film transistor fabrication process, the charge is dispersed through the corresponding common line. This reduces any sudden current which may flow between adjacent scanning lines or signal lines. This also reduces the possibility of breaking of a specific line or a change in the characteristics of a specific thin film transistor.
In the thin film transistor array as described above, however, no images can be displayed if the scanning lines 3 and the signal lines 4 are kept connected. Therefore, at a certain point during the fabrication process it is necessary to disconnect the scanning lines 3 and the signal lines 4 from their common lines to separate these lines from each other. Accordingly, when the lines are separated in, e.g., the step of cutting out a liquid crystal display panel from the glass substrate, the possibility that defects occur increases if static electricity applies large electric charge to the scanning lines or signal lines in the subsequent steps. More specifically, in the active matrix display test step, a probe or the like of a display test apparatus is brought into contact with each scanning line input pad 21 and each signal line input pad 22. The respective predetermined electrical signals are applied to the scanning line 3 and the signal line 4 to allow the active matrix display to display an image, thereby checking whether there is a defect. If a potential difference is produced between the probe of the display test apparatus and the scanning line input pad 21 or the signal line input pad 22, electric charge is applied to the thin film transistor array through the scanning line input pad 21 or the signal line input pad 22. This breaks or short-circuits the lines or breaks the insulating film. Alternatively, electric charge is injected into the gate insulating film in a transistor portion. Consequently, the threshold value shifts, and a defect such as a point defect takes place. Additionally, in the step of, e.g., mounting an external driving circuit, similar defects occur if a potential difference is produced between the scanning line input pad 21 or the signal line input pad 22 and the apparatus in contact with the pad.
One technique for solving the above problems is the structure of an active matrix display thin film transistor array disclosed in Japanese Unexamined Patent Publication No. 63-220289. FIG. 5 is a plan view showing an outline of the circuit configuration of this thin film transistor array. FIG. 6 shows two-terminal thin film transistors connected to one scanning line in the circuit configuration shown in FIG. 5.
As shown in FIGS. 5 and 6, in the thin film transistor array disclosed in Japanese Unexamined Patent Publication No. 63-220289, each scanning line 3 is connected to a reference potential line 25 by two two-terminal thin film transistors 28 and 29 connected antiparallelly. Similarly, each signal line 4 is connected to the reference potential line 25 by two two-terminal thin film transistors 26 and 27 connected antiparallelly. A driving circuit applies electrical signals to the scanning lines 3 and the signal lines 4 to operate display thin film transistors 5 formed at the intersections of the scanning lines 3 and the signal lines 4, thereby displaying images. A terminal (not shown) applies the same potential as applied to a common electrode of the liquid crystal display to the reference potential line 25. When the potential of the reference potential line 25 is made equal to the potential applied to the common electrode as described above, the reference potential line 25 can also be used as a line for applying the potential to the common electrode.
FIG. 7 shows the voltage-current characteristic of the scanning line 3 and the reference potential line 25 when two such two-terminal thin film transistors are added. That is, if the scanning line 3 is positively or negatively charged with respect to the reference potential line 25 by static electricity or the like during the thin film transistor array fabrication process, a current flows in a direction in which this electric charge is canceled. That is, if the scanning line 3 is positively charged, a current flows in a direction in which this positive charge is let go to the reference potential line 25. If the scanning line 3 is negatively charged, a current flows in a direction in which this negative charge is let go to the reference potential line 25. This decreases the potential difference between the charged scanning line 3 and the reference potential line 25 and the potential difference between the charged scanning line 3 and an adjacent scanning line 3. Accordingly, it is possible to reduce defects such as breaking of the insulating film at the intersection between the charged scanning line 3 and the reference potential line 25, breaking of the charged scanning line 3, a short circuit between the charged scanning line 3 and the adjacent scanning line 3, and shift of the threshold value of the display thin film transistor 5 connected to the charged scanning line 3. This similarly holds true for the signal line 4.
Also, in the active matrix display test step or the step of mounting an external driving circuit, if a potential difference is produced between the probe or the apparatus and the scanning line input pad 21 or the signal line input pad 22 and electric charge is applied to the thin film transistor array, this electric charge goes to the reference potential line 25. Consequently, defects occurring after the display test step can be reduced. Furthermore, these two-terminal thin film transistors 26, 27, 28, and 29 are formed in the same steps as the display thin film transistors 5. Therefore, an active matrix display not having many defects resulting from static electricity can be formed without adding new fabrication steps.
Unfortunately, the thin film transistor array of the active matrix display as described above has the problem that even when the active matrix display for displaying images is normally driven, a current flows between the reference potential line 25 and the scanning lines 3 through the two-terminal thin film transistors to increase the consumption power of the liquid crystal display.
Generally, a current I(A) flowing through a two-terminal thin film transistor is represented by EQU I=0 when V&lt;Vth,
or EQU I=K(V-Vth).sup.2 when V.gtoreq.Vth (1)
where
K is a constant (K=TC1W/2L), PA1 V is (source (drain) electrode potential)-(gate electrode potential), PA1 Vth is the threshold voltage of the two-terminal thin film transistor, PA1 T is the field-effect mobility, PA1 W is the transistor length, PA1 L is the transistor width, and PA1 C1 is the gate capacitance of the transistor.
Assume that in the above thin film transistor array, the voltage to be applied to the scanning line to turn on the display thin film transistor 5 is +20 V, the voltage to be applied to turn off the display thin film transistor 5 is -5 V, the voltage of the reference potential line 25 is the same voltage, +5 V, as applied to the common electrode, and Vth of the two-terminal thin film transistor is 2 V.
Assume also that this active matrix display is an SVGA panel (the number of signal lines=2,400, the number of scanning lines=600). When the display thin film transistor 5 connected to a certain scanning line 3 is ON, a voltage of +20 V is applied to this scanning line 3, and a voltage of -5 V is applied to the 599 remaining scanning lines. A current flowing between the scanning line 3 and the reference potential line 25 will be considered with reference to FIG. 6.
When a voltage of -5 V is applied to a certain scanning line 3, the two-terminal thin film transistor 28 is OFF, so no current flows. However, the two-terminal thin film transistor 29 is ON, so a current flows from the reference potential line 25 to the scanning line 3. This current I is I=(10-2).sup.2 K=64K from equation (1). Accordingly, letting I.sub.OFF be the sum of currents flowing between the 599 scanning lines 3 and the reference potential line 25, hd OFF=599.times.64K=38,336K(A).
When a voltage of +20 V is applied to a certain scanning line 3, the two-terminal thin film transistor 29 is OFF, so no current flows. However, the two-terminal thin film transistor 28 is ON, so a current flows from the scanning line 3 to the reference potential line 25. Letting I.sub.ON be this current, I.sub.ON =(15-2).sup.2 K=169K from equation (1). Since I.sub.OFF &gt;&gt;I.sub.ON, the current flowing between the scanning line 3 and the reference potential line 25 can be regarded as nearly I.sub.OFF. As described above, the thin film transistor array structure shown in FIG. 5 has the problem that the consumption power increases when the active matrix display is driven.